To improve the acquisition speed and performance of a typical GPS receiver, new receiver channels or additional correlator blocks within each channel are added. Such additions maximize the number of parallel searches that can be performed at any given time. Adding new receiver channels or correlator blocks within each channel generally leads to one of two tradeoffs. First, the GPS receiver can maintain flexibility by implementing the required logic in large and complex Field Programmable Gate Arrays (FPGAs) with adequate resources at a very high recurring cost of at least $2000 to $3000 per part. The GPS receiver can also sacrifice flexibility and scalability for cost savings by implementing the design in a custom fabricated multi-million gate or Application Specific Integrated Circuit (ASIC), with tremendous non-recurrent engineering costs.